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SPACETIME MEMORY
Spacetime memory architecture, like Spacetime logic architecture, has the dual advantage of higher capability and higher density. Block memories in FPGA architectures are dual-port. These dual-port memories are implemented using dual-port memory cells which are about twice the physical size of single-port memory cells. Spacetime memory architecture allows the use of single-port memory cells while providing eight memory ports. The LRAM memory, for example, uses single-port memory cells, that with eight folds, enables eight accesses per user clock cycle. This is shown in Figure 5. The single LRAM physical port can be accessed eight times in an eight-fold design with the port changing between Read/Write as required.
Therefore, Spacetime memory has several advantages:
- Higher density: Multi-port capability from (physical) single-port cells
- Higher port count and bandwidth: 8 to 16 ports
- Higher utilization: Ports can utilize separate address spaces
The use of single-port cell to deliver 8-port memories results in twice the memory density compared to FPGAs.
64-bit data input to the Tabula device can be written in four folds in a narrow 16-bit wide single-port memory instead of requiring a large 64-bit wide data path and memory port.
Memory configuration can change on each Subcycle.
There are a number of ways memories can be used in Spacetime.
Figure 6 is an example of LRAM memory used in a dual-port configuration enabled by Spacetime folding. Memory space is shared between the two Spacetime ports, with fold 0 being a Write port changed to a Read port for fold 1.
Figure 7 is an example of LRAM used with eight folds to implement four R/W ports with their own memory spaces.
Figure 8 is one example of the many ways Spacetime memory can be configured for broadcasting data. Data written to LRAM can be read by an agent on each fold, enabling broadcast to as many as seven agents for each user clock cycle.
